I build and evaluate next-generation compute platforms through chiplet systems modelling, hardware modelling, and design prototyping. My work spans emerging silicon solutions, novel architecture exploration, and full-system evaluation across simulation and emulation.
I completed my Ph.D. at the Indian Institute of Technology, Kharagpur. I was a member of the Secured Embedded Architecture Laboratory (SEAL), and I was supervised by Prof. Debdeep Mukhopadhyay. My research centered on efficient encrypted information retrieval and resilient hardware architectures for high-performance outsourced encrypted data processing.
Core Work Areas
Hardware and System Modelling
Chiplet System Modelling, Compute System Modelling, Interconnect Modelling, Algorithms to Architecture/RTL.
Cryptographic Hardware Design
Cryptographic Compute Cores, Cryptographic Accelerators, Side Channel Analysis, PUFs.
ASIC / FPGA Design
RTL Design and Verification, ASIC Frontend and Backend Flows, FPGA Prototyping.
Encrypted Domain Computation
Searchable Symmetric Encryption, Privacy-preserving Computation.