About Me

I am an R&D Engineer specializing in Cryptography and Hardware Security, currently working at imec, Belgium. I completed my Ph.D. as an Institute Research Fellow in the Department of Computer Science and Engineering at the Indian Institute of Technology, Kharagpur, within the Secured Embedded Architecture Laboratory (SEAL).

My background spans across the intersection of hardware designs, cryptosystems, and robust processing platforms, aiming to mitigate sophisticated threat models in modern architecture environments.

Research & Core Interests

Cryptography Hardware Security VLSI Design & Architecture Side-Channel Analysis Quantum Computation Quantum Cryptography Encrypted Domain Computation

Timeline

Present
R&D Engineer
imec · Leuven, Belgium
2017 — 2022
Ph.D. Research Scholar
Indian Institute of Technology, Kharagpur

Supervised by Prof. Debdeep Mukhopadhyay at SEAL Lab. Focused on Hardware Security and Cryptographic Implementations.

May 2015 — Apr 2015
Summer Research Intern
National Remote Sensing Centre, ISRO · Hyderabad, India

Designed a custom PLL-based clock recovery system for indigenous satellite downlink demodulators.

2012 — 2017
B.Tech. + M.Tech. Dual Degree
Indian Institute of Technology, Kharagpur

Electronics and Electrical Communication Engineering (CGPA: 8.23).

Selected Publications

Poster: Multi-Client and Quantum-Resilient Searchable Symmetric Encryption
IEEE Symposium on Security and Privacy (S&P), 2024
Fault Template Attacks on Block Ciphers Exploiting Fault Propagation
IACR Conference, Eurocrypt, 2020 (Zagreb, Croatia)
Enhancing Fault Tolerance of Neural Networks for Security-Critical Applications
ACM/IEEE Design Automation Conference (DAC Poster), 2019 (Las Vegas, USA)
Hardware Acceleration for Searchable Encryption
ACM CCS Poster, 2018 (Toronto, Canada)
Cryptographically Secure Multi-Tenant Provisioning of FPGAs
ACM/IEEE Design Automation Conference (DAC Poster), 2018 (San Francisco, USA)
Fault-Tolerant Implementations of Physically Unclonable Functions on FPGA
Book Chapter | Security and Fault Tolerance in Internet of Things, Springer Nature, 2019

Honors & Achievements

  • Winner of HACK@DAC '18: Part of the winning team at the prominent hardware security contest held in San Francisco, CA, USA concurrently with ACM/IEEE DAC 2018. Task involved identifying security vulnerabilities and bugs in the Pulpino RISC-V Core.
  • GeoAware Competition Winner (2014): Created an autonomous maze solver robot at Kshitij, IIT Kharagpur.

Tools & Toolchains

Xilinx Vivado Synopsys Design Compiler Synopsys IC Compiler Cadence Virtuoso Verilog C++ Python TCL
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